#define CREG_BASE   0xbfd00000
#define CLOCK_CTRL0 0x220
#define CLOCK_CTRL2 0x228
#define CHIP_SAMPLE0 0x210

#if 0	//mtf
sbc_pll_cfg:
	li	t0, CREG_BASE
	//      [12]sel, [11]pd, [10:8]odf, [7:1]ldf, [0]set
	//         25MHz            0      40*3(0x78)  0
	li	t1,  0x8f0
	sw	t1,  CLOCK_CTRL2(t0)
	li	t1,  0x8f1
	sw	t1,  CLOCK_CTRL2(t0)
	li	t2, 0x3
1:	bnez	t2, 1b
	addiu	t2, t2, -1
	li	t1,  0x0f1           // power up pll
	sw	t1,  CLOCK_CTRL2(t0)
	// wail lock
	li	t2, 0x40
1:	bnez	t2, 1b
	addiu	t2, t2, -1
	// TODO: read till lock...
	li	t1,  0x10f1		// select pll clk
	sw	t1,  CLOCK_CTRL2(t0)
	li	t1,  0x10f0		// clear set bit
	sw	t1,  CLOCK_CTRL2(t0)
#endif	//mtf

#if 0	//mtf
cpu_ddr_pll_cfg:
	li	t0, CREG_BASE
	//ddr	[31:24]ldf, [23:22]odf, [21:19]idf, [18]pd, [17]sel, [16]set
	//   25MHz  48(0x30)      3          1         0        0         0  -> 200MHz
	//cpu	[12]sel, [11]pd, [10:8]odf, [7:1]ldf, [0]set
	//   25MHz  0        0         3        32(0x20)  -> 100MHz
 	//   ldf    odf idf pd sel set - sel pd odf  ldf   set
	// 00100000 11 000  0   0   0 000 0   0 011 0100000 0
	//li	t1,  0x30c80340
	li	t1,  0x30cc0b40
	sw	t1,  CLOCK_CTRL0(t0)
	li	t1,  0x30cd0b41		// power down
	sw	t1,  CLOCK_CTRL0(t0)
	li	t2, 0x10
1:	bnez	t2, 1b
	addiu	t2, t2, -1
	li	t1,  0x30c90341		// power up
	sw	t1,  CLOCK_CTRL0(t0)
	// wail lock
	li	t2, 0x400
1:	bnez	t2, 1b
	addiu	t2, t2, -1
	// TODO: read till lock...
	li	t1,  0x30cb1341		// select pll clk
	sw	t1,  CLOCK_CTRL0(t0)
	li	t1,  0x30ca1340		// clear set bit
	sw	t1,  CLOCK_CTRL0(t0)
#endif	//mtf

